W3E32M72S-XBX
White Electronic Designs
after VCCQ to avoid device latch-up, which may cause
permanent damage to the device. VREF can be applied any
time after VCCQ but is expected to be nominally coincident
with VTT. Except for CKE, inputs are not recognized as
valid until after VREF is applied. CKE is an SSTL_2
input but will detect an LVCMOS LOW level after VCC is
applied. After CKE passes through VIH, it will transition to
an SSTL_2 signal and remain as such until power is cycled.
Maintaining an LVCMOS LOW level on CKE during power-
up is required to ensure that the DQ and DQS outputs will
be in the High-Z state, where they will remain until driven
in normal operation (by a read access). After all power
supply and reference voltages are stable, and the clock
is stable, the DDR SDRAM requires a 200µs delay prior
to applying an executable command.
FIGURE 2 – FUNCTIONAL BLOCK DIAGRAM
CS
B
#
WEB
#
RAS
CAS
B#
B#
CS# WE# RAS# CAS#
VREF
V
REF
DQ
0
DQ
0
A0-12
A
0-12
=
Y
=
Y
Y
BA
0
-1
BA0-1
=
Y
=
CK
CK
CKE
0
CK
CK#
CKE
DQML
DQMH
=
Y
=
Y
U0
0
#
B
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
DM
DM
0
1
0
1
DQ15
DQ15
DQS
DQS
DQSL
DQSH
CS# WE# RAS# CAS#
V
REF
Once the 200µs delay has been satisfied, a DESELECT
or NOP command should be applied, and CKE should
be brought HIGH. Following the NOP command, a
PRECHARGE ALL command should be applied. Next a
LOAD MODE REGISTER command should be issued for
the extended mode register (BA1 LOW and BA0 HIGH)
to enable the DLL, followed by another LOAD MODE
REGISTER command to the mode register (BA0/BA1
both LOW) to reset the DLL and to program the operating
parameters. Two-hundred clock cycles are required
between the DLL reset and any READ command. A
PRECHARGE ALL command should then be applied,
placing the device in the all banks idle state.
A
0-12
DQ
0
DQ16
=
Y
=
Y
=
Y
BA0-1
=
Y
CK
CK
CKE
DM
DM
DQS
DQS
1
CK
CK#
CKE
DQML
DQMH
DQSL
DQSH
=
Y
=
Y
U1
1
#
B
=
Y
=
Y
=
=
Y
Y
=
=
Y
Y
2
3
2
3
DQ15
DQ31
CS# WE# RAS# CAS#
V
REF
DQ
0
DQ32
A
0-12
=
=
Y
Y
BA0-1
CK
CK#
=
Y
=
Y
CK
2
=
Y
=
Y
U2
CK
2
#
=
Y
=
Y
CKE
B
CKE
=
=
Y
Y
=
=
Y
Y
DM
DM
DQS
DQS
4
5
DQML
DQMH
DQSL
DQSH
DQ15
DQ47
4
5
Once in the idle state, two AUTO REFRESH cycles must
be performed (tRFC must be satisfied.)Additionally, a LOAD
MODE REGISTER command for the mode register with
the reset DLL bit deactivated (i.e., to program operating
parameters without resetting the DLL) is required.
Following these requirements, the DDR SDRAM is ready
for normal operation.
CS# WE# RAS# CAS#
V
A
REF
DQ
0
DQ48
0-12
=
=
Y
Y
BA0-1
CK
CK#
CKE
DQML
DQMH
DQSL
DQSH
=
Y
=
Y
=
Y
CK
CK
CKE
3
=
Y
U3
=
Y
=
Y
3
#
=
=
Y
Y
B
=
=
Y
Y
DM
DM
DQS
DQS
6
7
6
7
DQ15
DQ63
CS# WE# RAS# CAS#
V
A
REF
DQ
0
DQ64
0-12
=
=
Y
Y
BA0-1
CK
CK#
CKE
DQML
DQMH
=
Y
=
Y
CK
CK
CKE
4
=
Y
=
Y
U4
=
Y
4
#
B
Y
=
=
=
Y
Y
=
=
Y
Y
DM
DM
8
9
DQ15
DQ79
DQS
DQS
8
9
DQSL
DQSH
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 2
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
