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SCA61T-FAHH1G 参数 Datasheet PDF下载

SCA61T-FAHH1G图片预览
型号: SCA61T-FAHH1G
PDF下载: 下载PDF文件 查看货源
内容描述: [Analog Circuit,]
分类和应用:
文件页数/大小: 18 页 / 308 K
品牌: VTI [ VTI TECHNOLOGIES ]
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SCA61T Series  
2.6 Self Test and Failure Detection Modes  
To ensure reliable measurement results the SCA61T has continuous interconnection failure and  
calibration memory validity detection. A detected failure forces the output signal close to power  
supply ground or VDD level, outside the normal output range. The normal output ranges are:  
analog 0.25-4.75 V (@Vdd=5V) and SPI 102...1945 counts.  
The calibration memory validity is verified by continuously running parity check for the control  
register memory content. In the case where a parity error is detected the control register is  
automatically re-loaded from the EEPROM. If a new parity error is detected after re-loading data  
both analog output voltage is forced to go close to ground level (<0.25 V) and SPI outputs goes  
below 102 counts.  
The SCA61T also includes a separate self test mode. The true self test simulates acceleration, or  
deceleration, using an electrostatic force. The electrostatic force simulates acceleration that is high  
enough to deflect the proof mass to the extreme positive position, and this causes the output signal  
to go to the maximum value. The self test function is activated either by a separate on-off  
command on the self test input, or through the SPI.  
The self-test generates an electrostatic force, deflecting the sensing element’s proof mass, thus  
checking the complete signal path. The true self test performs following checks:  
Sensing element movement check  
ASIC signal path check  
PCB signal path check  
Micro controller A/D and signal path check  
The created deflection can be seen in both the SPI and analogue output. The self test function is  
activated digitally by a STX command, and de-activated by a MEAS command. Self test can be  
also activated applying logic”1” (positive supply voltage level) to ST pin (pins 6) of SCA61T. The  
self test Input high voltage level is 4 – Vdd+0.3 V and input low voltage level is 0.3 – 1 V.  
ST pin  
5 V  
voltage  
0 V  
5V  
V1  
V2  
T1  
V3  
Vout  
T2  
T3  
0 V  
T4  
T5  
Figure 12.  
Self test wave forms  
V1 = initial output voltage before the self test function is activated.  
V2 = output voltage during the self test function.  
V3 = output voltage after the self test function has been de-activated and after stabilization time  
Please note that the error band specified for V3 is to guarantee that the output is within 5% of the  
initial value after the specified stabilization time. After a longer time (max. 1 second) V1=V3.  
T1 = Pulse length for Self test activation  
T2 = Saturation delay  
T3 = Recovery time  
T4 = Stabilization time =T2+T3  
T5 = Rise time during self test.  
Self test characteristics:  
VTI Technologies Oy  
www.vti.fi  
Subject to changes  
Doc. nr. 8261900  
13/18  
Rev.A  
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