SCA8X0/21X0/3100 Series
•
Specified operation voltage (VDD) range 3.05...3.6 V
6
To achieve high EMC DPI performance, add serial inductance (L1) to VDD line
before serial resistance (for example Murata: BLM18HG102S)
VDD
Note 1
L1
R1
10 Ω
SCA8x0
SCA21x0
SCA3100
C6
10 µF
1
2
3
4
5
6
12
11
10
9
NC
EGND
NC
DVSS
DVDD
PWM
C5
AVSS
AVDD
C4
100 nF
100 nF
8
CSB
MOSI
SCK
MOSI
SCK
CSB
7
MISO
MISO
Figure 9: Recommended circuit diagram
6.6 Recommended PWB layout
Recommended PWB layout for all product family components with SPI interface is shown in Figure
10 and Figure 11. Following design rules and recommendations should be considered:
Required:
1
2
3
Connect (C4) 100 nF SMD capacitor between AVDD and AVSS right next to
component pins AVDD and AVSS
Connect (C5) 100 nF SMD capacitor between DVDD and DVSS right next to
component pins DVDD and DVSS
Use separate ground levels AVSS and DVSS under and near the component
but connect them together on the PCB, see Figure 10
Locate ground plate under component
Do not route signals or power supplies under the component on top layer
Ensure good ground connection of Egnd (pin12) to AVSS
4
5
6
Recommended:
7
8
9
Locate digital ground under digital signal lines
Do not route digital signals one upon the other for long distance
Avoid crossing of AVDD path with digital signal especially between serial
resistance R1 and AVDD pin
10 Do not route digital signals under the component on 2nd layer
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