CMA3000-D0X Series
9.1.2 Acceleration reading without interrupts
Acceleration data reading without interrupts can be used in all operation modes. Acceleration data
is read out faster than CMA3000 can updates the acceleration output registers. When two identical
XYZ acceleration values are received, the data is considered valid. The maximum data reading
periods in different operation modes are presented below in Table 13.
Table 13. CMA3000-D01 maximum reading periods when interrupts are not detected.
Maximum reading period
Output data rate
for 3 samples, Tr
CMA3000-D01, MODE bits x10
ODR: 400Hz
2.4 ms
CMA3000-D01, MODE bits x01
ODR: 100Hz
9.9 ms
CMA3000-D01, MODE bits 011
ODR: 40Hz
24.0 ms
CMA3000-D01, MODE bits 100
ODR: 10Hz
ODR = Output Data Rate
90.0 ms
Internal acceleration
register update
These two acceleration readings result identical
Internal acceleration
register update
acceleration values → This result is accepted
Acceleration reading
Acceleration reading
Acceleration reading
Acceleration reading
→ corrupted
→ corrupted
Acceleration data reading period for 3 samples, Tr
Figure 25. Interrupt based CMA3000 acceleration data read timing.
9.2 Leakage current when VDD - DVIO > 0.3 V
Due to design issue a switch will leak some current, if the VDD will be approx 300 mV higher than
DVIO. Typical leakage currents are according to the Table 14 below.
Table 14 CMA3000-D0X typical DVIO leakage current when VDD-DVIO>0.3V.
VDD/DVIO [V]
2.5 / 1.7
Leakage current [µA]
25
3.6 / 1.7
100
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