CMA3000-D0X Series
9
Known issues
9.1 Acceleration data reading via I2C bus
CMA3000-D01 has a design issue (to be corrected) related to acceleration data reading via I2C
bus: acceleration data reading during the INT-pin assertion (i.e. internal output register update)
causes the data corruption. The following sections discuss how to overcome this.
9.1.1 Interrupt based acceleration reading
Interrupt (INT-pin) based acceleration data reading can be used only in measurement mode. After
interrupt signal activation the acceleration data has to be read before next interrupt activation. The
allowed reading time depends on selected measurement mode. Detailed timing values are
presented in Table 12 and Figure 24 below.
Table 12. CMA3000-D01 maximum reading periods in interrupt based acceleration data reading.
Maximum reading
Output data rate
period, Tr
CMA3000-D01, MODE bits x10
ODR: 400Hz
2.25 ms
CMA3000-D01, MODE bits x01
ODR: 100Hz
9.0 ms
CMA3000-D01, MODE bits 011
ODR: 40Hz
ODR = Output Data Rate
22.5 ms
Acceleration reading ends
Interrupt activation
Interrupt activation
INT-pin
Reading period, Tr
Interrupt initialized
Figure 24. Interrupt based CMA3000 acceleration data read timing.
If the above presented data read timing constraints are not met, the acceleration output data
should be ignored. Valid data samples can be read after the next interrupt signal.
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