Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
VIS
Figure 6.3 Clock Suspension During Burst Read (Using CKE)
(Burst Length = 4, CAS Latency = 3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK3
CS
RAS
CAS
WE
DSF
BS
RAx
A9
A0 ~ A8
RAx
CAx
DQM
DQ
t
HZ
Hi-Z
Ax0
Ax1
Ax2
Ax3
Clock Suspend Clock Suspend
Clock Suspend
3 Cycles
Activate
Command
Bank A
Read
Command
Bank A
1 Cycle
2 Cycles
Note: CKE to CLK disable/enable = 1 clock
Document:
Rev.1
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