Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
VIS
Figure 7.3 Clock Suspension During Burst Write (Using CKE)
(Burst Length = 4, CAS Latency = 3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK3
CKE
CS
RAS
CAS
WE
DSF
BS
RAx
A9
A0 ~ A8
RAx
CAx
DQM
DQ
Hi-Z
DAx0
DAx1
DAx2
DAx3
Clock Suspend
1 Cycle
Activate
Command
Bank A
Clock Suspend
3 Cycles
Clock Suspend
2 Cycles
Write
Command
Bank A
Note: CKE to CLK disable/enable = 1 clock
Document:
Rev.1
Page11