VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary
CMOS Synchronous Graphic RAM
VIS
Figure 21. Burst Read and Single Write Operation (Burst Length = 4, CAS Latency = 2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
High
CK2
CKE
CS
RAS
CAS
WE
DSF
BS
A9
RAx
CAx
RAx
CAw
CAy
CAz
CAx
A0 ~ A8
DQM0
DQM1~3
DQ0 - DQ7
DQ8 - DQ31
Hi-Z
Ay1
Ay3
DQw0
DQw0
Ay0
Ay0
Az0
Az0
Ax0
Ax0
Ax3
Ax1
Ax2
Hi-Z
Ay2 Ay3
DQx0
Ax1 Ax2 Ax3
Lower Byte
is masked
Lower Byte
is masked
Read
Single Write
Command
Bank A
Single Write
Command
Bank A
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Upptr 3 Bytes
is masked
Single Write
Command
Bank A
Document:1G5-0145
Rev.1
Page73
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
