VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary
CMOS Synchronous Graphic RAM
VIS
Figure 20. Byte Write Operation (Burst Length = 4, CAS Latency = 2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
High
CK2
CS
RAS
CAS
WE
DSF
BS
RAx
A9
CAx
CAy
CAz
RAx
A0 ~ A8
DQM0
DQM1~3
DQ0 - DQ7
DQ8 - DQ31
Ax1 Ax2
DAy2
Ax0
Az2
Az2
DAy1
Az1
Hi-Z
Az0 Az1
Ax2 Ax3
DAy3
Az3
DAy0 DAy1
Ax1
Lower Byte
is masked
Lower Byte
is masked
Lower Byte
is masked
Activate
Command
Bank A
Read
Command
Bank A
Write
Read
Command
Command
Bank A
Upper 3 Bytes
are masked
Bank A
Upper 3 Bytes
are masked
Document:1G5-0145
Rev.1
Page72