VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary
CMOS Synchronous Graphic RAM
VIS
Figure 25. Full Page Random Column Write (Burst Length = Full Page, CAS Latency = 2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE
CS
RAS
CAS
WE
DSF
BS
RBw
RBw
RAx
RAx
RBx
RBx
A9
CAx
CBx
CAz
CBz
A0 ~ A8
CAy
CBy
tWR
tRP
DQM
DQ
tRRD
tRCD
DAz0
DAx0
DBy0 DBy1
DAz2
DBz2
DBx0 DAy0
DAz1
DBz1
DAy1
DBz0
Write
Command
Bank B
Write
Command
Bank A
Precharge
Command Bank B
(Precharge Termination)
Write
Command
Bank B
Activate
Command
Bank A
Write
Command
Bank B
Activate
Command
Bank B
Activate
Write Data
is masked
Command
Bank B
Write
Command
Bank A
Write
Command
Bank A
Document:1G5-0145
Rev.1
Page77
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
