VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary
CMOS Synchronous Graphic RAM
VIS
Figure 18.3. Full Page Read Cycle (Burst Length = Full Page, CAS Latency = 3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK3
High
CKE
CS
RAS
CAS
WE
DSF
BS
RBy
RBy
RAx
RAx
RBx
RBx
A9
CAx
CBx
A0 ~ A8
t
RP
DQM
DQ
Hi-Z
Ax-2
Ax
Ax+2
Ax-1
Bx+5
Bx+4
Ax+1
Ax+1
Bx+2 Bx+3
Bx+1
Ax
Bx
Read
Activate
Command
Bank B
Precharge
Command
Bank B
Command
Activate
Command
Bank B
Activate
Read
Bank B
Command
Command
Bank A
Burst Stop
Command
Bank A
Full Page burst operation does not terminate
when the burst length is satisfied; the burst
counter increments and continues bursting
beginning with the starting address.
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Document:1G5-0145
Rev.1
Page68