Preliminary
VG37648041AT
256M:x4, x8, x16
VIS
CMOS Synchronous Dynamic RAM
T0
T1
T10
T2
T3
T4
T5
T6
T7
T9
T11
T8
CLK#
CLK
COMMAND
ADDRESS
WRITE
NOP
NOP
NOP
PRE
NOP
tWR
Bank,
Bank a,
Col b
(a or all)
tDSS
max
tRP
DQS
DQ
Dl
b
DM
DONT’ CARE
UNDEFINED
Dl b=Data In for column b
3 subsequent elements of Data In are applied in the programmed order following Dl b
A non-interrupted burst of 4 is shown
tWTR is referenced from the first positive CLK edge after the last Data In pair
A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled)
Figure 28
WRITE TO PRECHARGE - MAX DSS, NON-INTERRUPTING
Document : 1G5-0157
Rev.1
Page54