VG36644041DT / VG36648041DT / VG36641641DT
CMOS Synchronous Dynamic RAM
VIS
Full Page Random Column Read
Burst Length=Full Page, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE
CS
RAS
CAS
WE
BS
Ra
Ra
Ra
Ra
Rb
Rb
A10
Ca
Ca
Cc
Cc
Cb
Cb
ADD
t
RP
DQM
DQ
Hi-Z
QBb1 QAc0
QAc2
QAa0 QBa0
QBb0
QAc1
QBc1 QBc2
QAb0 QAb1
Read
QBc0
Read
Precharge
(Bank D)
Read
Read
Activate
Command
Bank A
Activate
Command
Bank B
Command Bank B
(Precharge Termination)
Command
Bank B
Command
Bank B
Command
Bank A
Command
Bank B
Activate
Command
Bank B
Read
Command
Bank A
Read
Command
Bank A
* BS1=”L”, Bank C,D = Idle
Document :1G5-0177
Rev.2
Page65
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
