VG36644041DT / VG36648041DT / VG36641641DT
CMOS Synchronous Dynamic RAM
VIS
Full Page Read Cycle (2 of 2)
Burst Length=Full Page, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK3
High
CS
RAS
CAS
WE
*BS0
A10
Ra
Rb
Rb
Ra
Ra
Ca
Ra
Ca
ADD
DQM
Hi-Z
QBa+3
QBa+4
QBa+5
QAa-2
QAa+1
QBa+1
QBa+2
QAa+2
QAa
QBa0
QAa QAa+1
QAa-1
Read
DQ
Full page burst operation
does not teminate when
Read
Command
Bank A
Activate
Activate
Command
Bank A
Precharge
Command
Bank B
Activate
Command
Bank B
Command
Bank B
Command
Bank B
the burst length is satisfied;
the burst counter increments
and continues bursting
beginning with the starting
address
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Burst Stop
Command
* BS1=”L”, Bank C,D = Idle
Document :1G5-0177
Rev.2
Page61
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
