VG36644041DT / VG36648041DT / VG36641641DT
CMOS Synchronous Dynamic RAM
VIS
10.2.2 Precharge Termination in WRITE Cycle
During WRITE cycle, the burst write operation is terminated by a precharge command.
When the precharge command is issued, the burst write operation is terminated and precharge starts.
The same bank can be activated again after tRP from the precharge command. The DQM must be high to mask
invalid data in.
During WRITE cycle, the write data written prior to the precharge command will be correctly stored. However,
invalid data may be written at the same clock as the precharge command. To prevent this from happening, DQM
must be high at the same clock as the precharge command. This will mask the invalid data.
PRECHARGE TERMINATION in WRITE Cycle
Burst lengh = X
T0
T1
T3
T6
T8
T2
T4
T5
T7
CLK
Write
PRE
ACT
Command
CAS latency = 2
DQM
Hi - Z
DQ
D0
D3
D2
D4
D1
tRP
command
Write
PRE
ACT
CAS latency = 3
DQM
Hi - Z
tRP
DQ
D0
D3
D2
D4
D1
Document :1G5-0177
Rev.2
Page27
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
