VG36644041DT / VG36648041DT / VG36641641DT
CMOS Synchronous Dynamic RAM
VIS
9.3 Write to Read Command Interval
The write command to read command interval is also a minimum of 1 cycle. Only the write data before the read command
will be written. The data bus must be Hi-Z at least one cycle prior to the first D
.
OUT
WRITE to READ Command Interval
Burst lengh=4
T7
T0
T1
T3
T6
T8
T2
T4
T5
CLK
1 cycle
Read B
Command
WRITE A
CAS latency=2
Hi-Z
DA0
QB0
QB1
QB2
QB3
DQ
Write A
DA0
Command
Read B
CAS latency=3
Hi-Z
QB0
QB1
QB3
QB2
DQ
9.4 Read to Write Command Interval
During a read cycle, READ can be interrupted by WRITE.
DQM must be in High at least 3 clocks prior to the write command. There is a restriction to avoid a data conflict. The data
bus must be Hi-Z using DQM before Write.
Document :1G5-0177
Rev.2
Page23
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
