Preliminary
VG36648041CT
CMOS Synchronous Dynamic RAM
VIS
Full Page Random Column Write
Burst Length=Full Page, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE
CS
RAS
CAS
WE
BS
Ra
Ra
Ra
Ra
Rb
Rb
A10
Ca
Ca
Cc
Cc
Cb
Cb
ADD
DQM
DQ
t
RP
Hi-Z
QAc0
QAa0
QBb0 QBb1
QAc2
QBc2
QBa0 QAb0
QAc1
QBc1
QAb1
QBc0
Write
Command
Bank B
(Bank D)
Write
Command
Bank B
(Bank D)
Precharge
Command Bank B
(Precharge Termination)
Write
Command
Bank A
Write
Command
Bank B
(Bank D)
Activate
Command
Bank A
Activate
Command
Bank B
(Bank D)
(Bank D)
Activate
Command
Bank B
(Bank D)
Write Data
is masked
Write
Write
Command
Bank A
Command
Bank A
Document : 1G5-0153
Rev.1
Page67
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
