Preliminary
VG36648041CT
CMOS Synchronous Dynamic RAM
VIS
Full Page Write Cycle (1 of 2)
Burst Length=Full Page, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK2
High
CS
RAS
CAS
WE
BS
Ra
Rb
Rb
Ra
Ra
A10
Ca
Ra
Ca
ADD
DQM
t
BDL
Hi-Z
QAa+1
QBa+1
QBa+2
QAa
QBa
QBa+4
QBa+6
QBa+5
QAa QAa+1
QAa-1
QBa+3
DQ
QAa+2 QAa+3
Activate
Write
Data is ignored
Write
Activate
Command
Bank A
Activate
Command
Bank B
(Bank D)
Command
Bank B
Precharge
Command
Bank B
Command
Bank A
Command
Bank B
(Bank D)
(Bank D)
(Bank D)
Burst Stop
Command
Full page burst operation
does not terminate when
the burst length is satisfied;
the burst counter increments
and continues bursting
beginning with the starting
address
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Document : 1G5-0153
Rev.1
Page62
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
