Preliminary
VG36648041CT
CMOS Synchronous Dynamic RAM
VIS
Full Page Read Cycle (2 of 2)
Burst Length=Full Page, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK3
High
CS
RAS
CAS
WE
BS
Ra
Rb
Rb
Ra
Ra
A10
Ca
Ra
Ca
ADD
DQM
Hi-Z
QBa+3
QBa+4
QBa+5
QAa-2
QAa+1
QBa+1
QBa+2
QAa+2
QAa
QBa0
QAa QAa+1
QAa-1
Read
DQ
Full page burst operation
does not teminate when
Read
Command
Bank A
Activate
Activate
Command
Bank A
Precharge
Command
Bank B
(Bank D)
Activate
Command
Bank B
(Bank D)
Command
Bank B
(Bank D)
Command
the burst length is satisfied;
the burst counter increments
and continues bursting
beginning with the starting
address
Bank B
(Bank D)
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Burst Stop
Command
Document : 1G5-0153
Rev.1
Page61