Preliminary
VG36641641BT
CMOS Synchronous Dynamic RAM
VIS
Interleaved Column Read Cycle (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE
CS
RAS
CAS
WE
BS
Ra
Ra
Ra
Ra
A10
Ca
Cb
Cc
Cb
Cd
Cb
ADD
t
t
DQM
AC2
RCD
Hi-Z
QBa0
Read
QBc0
QBc1 QAb0 QAb1 QBd0 QBd1
QAa3
QBa1 QBb0 QBb1
QAa0 QAa1
QBd2 QBd3
QAa2
DQ
Activate
Command
Bank A
Read
Command
Bank A
Read
Command
Bank B
Read
Activate
Command
Bank B
Read
Command
Bank B
Read
Precharge
Command
Bank B
Command
Command
Bank B
(Bank D)
Command
Bank A
Bank B
(Bank D)
(Bank D) (Bank D)
(Bank D)
(Bank D)
Precharge
Command
Bank A
Document : 1G5-0127
Rev2
Page52
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
