VG36644041DT / VG36648041DT / VG36641641DT
CMOS Synchronous Dynamic RAM
VIS
Random Row Read (Interleaving Banks) (2 of 2)
Burs tLength=8, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK3
High
CS
RAS
CAS
WE
*BS0
A10
ADD
t
t
t
AC3
RP
RCD
DQM
Hi-Z
QBa5
Read
QBa0
QBa4
QBa6 QBa7 QAa0 QAa1 QAa2
QBb0
QAa7
QBa2
QAa4
QBa1
QAa3
QAa6
QBa3
QAa5
Read
DQ
Read
Command
Bank B
Activate
Command
Bank B
Precharge
Command
Bank B
Activate
Command
Bank A
Activate
Command
Bank B
Precharge
Command
Bank A
Command
Bank A
Command
Bank B
* BS1=”L”, Bank C,D = Idle
Document :1G5-0177
Rev.2
Page47
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
