VG3617161ET
1,048,576 x 16 - Bit
CMOS Synchronous Dynamic RAM
VIS
6. Power-up sequence is described in Note 10.
7. A.C. Test Conditions
Reference Level of Output Signals
Output Load
1.4V
Reference to the Under Output Load (B)
Input Signal Levels
2.4V / 0.4V
1ns
Transition Time (Rise and Fall) of Input Signals
Reference Level of Input Signals
1.4V
3.3V
1.4V
50
1.2K
W
W
ZO=50
W
Output
Output
30pF
30pF
870
W
LVTTL D.C. Test Load (A)
LVTTL A.C. Test Load (B)
8. Transition times are measured between VIH and VIL. Transition (rise and fall) of input signals are fixed slope (1 ns).
9. tHZ defines the time at which the outputs achieve the open circuit condition and are not reference levels.
10. Power up sequence
Power up must be performed in the following sequence.
1) Power must be applied to VDD and VDDQ (simultaneously) when all input signals are held “NOP” state and
CKE = ”H”, DQM = ”H”. The CLK signals must be started at the same time.
2) After power-up, a pause of 200u secouds minimum is required. Then, it is recommended that DQM is held
“high” (VDD levels) to ensure DQ output to be in the high impedance.
3) Both banks must be precharged.
4) Mode Register Set command must be asserted to initialize the Mode Register.
5) A minimum of 8 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the device. Sequence of
4 and 5 may be changed.
Document:1G5-0189
Rev.1
Page7
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
