VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
VIS
A.C. Characteristics (Ta = 0 ~ 70°C, V = V
= 3.3±0.3V , V = V
= 0V, unless otherwise noted)
DD
DDQ
SS
SSQ
Limits
Parameter
Symbol
-7H
-7L
-8H
Unit
Min
7.5
7.5
Max
Min
7.5
10
Max
Min
10
8
Max
CLK cycle time
CL = 3
CL = 2
CL = 3
CL = 2
tCK3
tCK2
tAC3
tAC2
tCH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
CLK to valid output delay
5.4
5.4
5.4
6
6
6
CLK high pulse width
CLK low pulse width
2.5
2.5
1.5
0.8
2.7
2.7
0
2.5
2.5
1.5
0.8
2.7
3
3
3
tCL
Input setup time (all input)
Input hold time (all input)
Output data hold time
tIS
2
tIH
1
CL = 3
CL = 2
tOH3
tOH2
tLZ
3
3
CLK to output in low - Z
CLK to output in H - Z
ROW cycle time
0
0
tHZ
5.4
5.4
2.7
67.5
45
15
15
14
14
1
2.7
67.5
45
20
20
15
15
1
3
6
tRC
70
50
20
20
20
20
1
ROW active time
tRAS
tRCD
tRP
100K
100K
100K
RAS to CAS delay
Row precharge time
Row active to active delay
Write recovery time
Transition time
tRRD
tWR
tT
10
64
10
64
10
64
Mode reg. set cycle
Power down exit setup time
Self refresh exit time
Refresh time
tRSC
tPDE
tSRX
tREF
14
7
15
7.5
7.5
20
10
10
7
Document :1G5-0183
Rev.1
Page8
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
