VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
VIS
9. Read / Writw Command Interval
9.1 Read to Read Command Interval
During a read cycle when a new read command is asserted, it will be effective after the CAS latency, even if the previ-
ous read operation has not completed. READ will be interrupted by another READ.
Each read command can be asserted in every clock without any restriction.
READ to READ Command Interval
Burst lengh=4, CAS latency=2
T0
T1
T3
T6
T2
T4
T5
T7
T8
CLK
Read B
Read A
Command
Hi-Z_
DQ
QA0
QB0
QB1
QB2
QB3
1 cycle
9.2 Write to Write Command Interval
During a write cycle, when a new Write command is asserted, the previous burst will terminated and the new burst will
begin with a new write command. WRITE will be interrupted by another WRITE.
Each write command can be asserted in every clock without any restriction.
WRITE to WRITE Command Interval
Burst lengh=4, CAS latency=2
T0
T1
T3
T6
T7
T2
T4
T5
T8
CLK
Write B
Write A
Command
Hi-Z_
QA0
QB0
DQ
QB1
QB2
QB3
1 cycle
Document :1G5-0183
Rev.1
Page21
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
