VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
VIS
8.2 Write with Auto Precharge
During a write cycle, the auto precharge starts at the timing that is equal to the value of tDPL(min.) after the last data
word input to the device.
WRITE with AUTO PRECHRGE
Burst lengh = 4
T0
T1
T3
T6
T8
T2
T4
T5
T7
CLK
Command
AUTO PRECHARGE starts
WRITA B
DB0
t
DPL
CAS latency = 2
Hi - Z_
DQ
DB2
DB3
DB1
AUTO PRECHARGE starts
Command
WRITA B
DB0
t
DPL
CAS latency = 3
Hi - Z
DQ
DB2
DB1
DB3
Remark WRITA means WRITE with AUTO Precharge
In summary, the auto precharge cycle begins relative to a reference clock that indicates the last data word is valid.
In the table below, minus means clocks before the reference; plus means clocks after the reference.
CAS latency
2
Read
-1
Write
+ tDPL(min.)
3
-2
+ tDPL(min.)
Document :1G5-0183
Rev.1
Page20
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
