VG26(V)(S)17400E
4,194,304 x 4 - Bit
CMOS Dynamic RAM
VIS
Read Cycle
VG26 (V) (S) 17400E
-5 -6
Unit
60 ns
Notes
Min
Max
50
Min
Max
Parameter
Symbol
tRAC
-
12
Access time from RAS
-
tCAC
tAA
13,14
14,15
Access time from CAS
-
-
13
25
13
-
-
-
15 ns
30 ns
15 ns
Access time from column address
Access time from OE
tOEA
tRCS
tRCH
tRRH
tOFF
tOEZ
-
-
7
10,16
16
Read command setup time
Read command hold time to CAS
Read command hold time to RAS
Output buffer turn-off time
0
0
0
0
0
0
0
0
0
0
-
-
-
ns
ns
ns
-
-
17
13
13
15 ns
ns
17
Output buffer turn-off time from OE
15
Write Cycle
VG26 (V) (S) 17400E
-5 -6
Unit
Notes
7,18
Min
Max
Min
Max
Parameter
Symbol
tWCS
Write command setup time
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data-in setup time
0
-
-
-
-
-
-
-
0
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
tWCH
tWP
8
8
10
10
15
10
0
tRWL
tCWL
tDS
13
8
19
19
0
ns
ns
tDH
Data-in hold time
8
10
Read - Modigy - Write Cycle
VG26 (V) (S) 17400E
-5 -6
Unit
Notes
Min
125
Max
Min
150
Max
Parameter
Symbol
tRWC
Read - modify - write cycle time
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
RAS to WE delay time
tRWD
tCWD
tAWD
tOEH
65
30
40
8
80
35
50
10
18
18
18
CAS to WE delay time
Column address to WE delay time
OE hold time from WE
ns
ns
Document : 1G5-0142
Rev.1
Page11
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
