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VG26S17400EJ-6 参数 Datasheet PDF下载

VG26S17400EJ-6图片预览
型号: VG26S17400EJ-6
PDF下载: 下载PDF文件 查看货源
内容描述: 4194304 ×4 - 位CMOS动态RAM [4,194,304 x 4 - Bit CMOS Dynamic RAM]
分类和应用:
文件页数/大小: 25 页 / 211 K
品牌: VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
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VG26(V)(S)17400E  
4,194,304 x 4 - Bit  
CMOS Dynamic RAM  
VIS  
AC Characteristics  
(Ta = 0 to + 70°C, VCC = 5V ±10% or 3.3V ±10%, VSS = 0V) * 1, * 2, * 3, * 4  
Test conditions  
• Output load : two TTL Loads and 100pF(VCC = 5.0V±10%)  
one TTL Load and 100pF(VCC = 3.3V±10%)  
• Input timing reference levels :  
VIH = 2.4V, VlL = 0.8V (VCC = 5.0V±10%); VIH = 2.0V, VlL = 0.8V (VCC = 3.3V±10%)  
• Output timing reference levels :  
VOH = 2.0V, VOL = 0.8V (VCC = 5V±10%, 3.3V±10%)  
Read, Write, Read - Modify - Write and Refresh Cycles  
(Common Parameters)  
VG26 (V) (S) 17400E  
-5  
-6  
Unit Notes  
Min  
90  
Max  
Min  
110  
Max  
Parameter  
Symbol  
tRC  
-
-
-
-
-
-
ns  
ns  
ns  
Random read or write cycle time  
RAS precharge time  
tRP  
tCPN  
tRAS  
tCAS  
tASR  
tRAH  
tASC  
tCAH  
tRCD  
tRAD  
tRAL  
tRSH  
tCSH  
tCRP  
tOED  
tT  
30  
10  
40  
10  
CAS precharge time in normal mode  
RAS pulse width  
50 10000  
12 10000  
10000 ns  
5
6
60  
15 10000 ns  
CAS pulse width  
0
8
-
0
10  
0
-
-
-
-
ns  
ns  
ns  
ns  
Row address setup time  
Row address hold time  
Column address setup time  
Column address hold time  
RAS to CAS delay time  
RAS to column address delay time  
Column address to RAS lead time  
RAS hold time  
-
0
-
7
8
-
10  
14  
12  
30  
15  
60  
5
12  
10  
25  
13  
50  
5
37  
45 ns  
30 ns  
8
9
25  
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
-
-
CAS hold time  
-
10  
11  
CAS to RAS precharge time  
OE to Din delay time  
12  
1
-
50  
32  
128  
-
15  
1
50 ns  
32 ms  
128 ms  
Transition time (rise and fall)  
Refresh period  
tREF  
tREF  
tCLZ  
tDZC  
tDZO  
-
-
-
-
Refresh period (S - Version)  
CAS to output in Low-Z  
CAS delay time from Din  
OE delay time from Din  
0
0
-
-
-
ns  
ns  
ns  
0
-
0
0
-
0
Document : 1G5-0142  
Rev.1  
Page10