128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
SIMPLIFIED STATE DIAGRAM
SELF
REFRESH
REFS
REFSX
MODE
REGISTER
SET
MRS
REFA
AUTO
IDLE
REFRESH
CKEL
CLK
CKEH
SUSPEND
ACT
POWER
DOWN
CKEL
CKEH
ROW
ACTIVE
TERM
READ
TERM
WRITE
WRITEA READA
CKEL
CKEH
CKEL
READ
WRITE
READ
WRITE
READ
SUSPEND
WRITE
SUSPEND
CKEH
READA
WRITEA
WRITEA
READA
PRE
CKEL
CKEH
CKEL
CKEH
READA
WRITEA
WRITEA
PRE
READA
SUSPEND
SUSPEND
PRE
POWER
APPLIED
PRE
POWER
ON
PRE
CHARGE
Automatic Sequence
Command Sequence
JULY.2000
Rev.2.2
Page-14