VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
High Performance Serial
Backplane Transceiver
VSC870
33 32
0 0
31 30 29 28 27 26 25
24 23 22 21 20
19 18 17 16
15 14 13 12
11 10 09 08
07 06 05 04
03 02 01 00
1 0 1 0
0 B B 1 0 1 0
1 0
B
R
M M M M
00 01 02 03
M M M M
04 05 06 07
M M M M
08 09 10 11
M M M M
12 13 14 15
D D D D
03 02 01 00
K
------ Active Connections ------
--Data--
Where:
B[1:0]00=Undefined,
01=Flow control channel,
10=Flow control channel,
11=Acknowledge
BRK1=This is the CRQ word for the next packet, 0=End of packet
M[0:15]Current outputs the transmit side is connected to
D[3:0] User defined data sent by transmitting port card
2.2.7 CRQ Word Format at the Transceiver RXOUT[31:0] Interface
This is the CRQ command word format on the parallel interface RXOUT[31:0] of the transceiver. The two
overhead bits are removed. This word arrives at the transceiver D words before the end of packet and also at the end
of packet. The BRK bit is used to designate the end of packet (see Application Note 31). The data bits D[3:0] can be
used by the transmitting port card to send information to the receiving port card such as port ID number.
31 30 29 28
0 0 0 0
27 26 25
0 0 0
24 23 22 21 20
19 18 17 16
15 14 13 12
11 10 09 08
07 06 05 04
03 02 01 00
0 0 0 0
B
M M M M
00 01 02 03
M M M M
04 05 06 07
M M M M
08 09 10 11
M M M M
12 13 14 15
D D D D
03 02 01 00
R
K
------ Active Connections ------
--Data--
Where:
BRK1=This is the CRQ word for the next packet, 0=End of packet
M[0:15]Current outputs the transmit side is connected to
D[3:0] User defined data sent by transmitting port card
2.3 Transmitter Operation
In Packet Mode, the transmitter is loaded with a connection request (CRQ) word followed by data words at the
parallel interface. The operation of the transceiver is such that a single CRQ word loaded into TXIN[31:0] may cause
the transceiver to send multiple CRQ words to the switch chip. When this happens, data may be blocked for several
word clocks until the switch grants the request. In order to improve bandwidth utilization, a system wide mode of
operation (called ‘early arbitration’) can be used where the switch matrix reconfiguration time is delayed D word
clocks from the time arbitration results are determined. This allows the user logic to receive arbitration results just as
the first word of the next data packet is ready for transmission, thus improving bandwidth utilization.
The CRQ word has several control bits that are shown in the definitions above. Five of these bits control the
operation of the transceiver. The mode bits MD[1:0] determine the transceiver operating mode for a particular
connection request. The control bits CT[2:0] determine priority levels or time-out values depending on the mode of
operation. A summary of these operating modes is shown below. All of these modes will operate with early
arbitration as described in the next sections.
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 16
G52190-0, Rev 4.1
01/05/01
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
