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VSC864A-2F 参数 Datasheet PDF下载

VSC864A-2F图片预览
型号: VSC864A-2F
PDF下载: 下载PDF文件 查看货源
内容描述: [Digital Time Switch, CQFP344, HEAT SINK, CAVITY-DOWN, CERAMIC, LDCC-344]
分类和应用: 电信电信集成电路
文件页数/大小: 12 页 / 107 K
品牌: VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
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VSC864A-2  
VITESSE  
Data Sheet  
200 Mb/s 64 x 64  
Crosspoint Switch  
Expandability  
The VSC864A-2 can be expanded to larger crosspoint switches by configuring it so that any input can be  
multiplexed to any output. The figure below is an example of a 128 x 128 crosspoint switch. The top two  
VSC864A-2s (1&2) correspond to the first 64 outputs and the bottom two VSC864A-2s (3&4) correspond to  
the last 64 outputs. The VSC864A-2s on the left (1&3) correspond to the first 64 inputs, and the two VSC864A-  
2s on the right (2&4) correspond to the last inputs. All like outputs are then joined to form a 128 bit Z output  
bus. The ability of the VSC864A-2 to tri-state its outputs will prevent contention on the Z bus.  
The TRI input is configured such that when it is active on the left hand chips (which are responsible for  
routing the first 64 inputs) it is inactive on the two right hand chips (which are responsible for routing the last 64  
inputs). The TRI input thus functions as the MSB of a 7-bit channel address word (A-bus plus TRI). Chips can  
share A-bus information. The destination (D) bus can be shared among the four chips with the local strobe for  
each device being used to select which output address gets reconfigured.  
The layout and placement of the VSC864A-2 is such that inputs are on the top and bottom of the chip and  
outputs are to the right and left. In this way a PC board design for a large crosspoint is facilitated.  
In the read mode tri-stateability on the Q-bus can be controlled with the TEST STROBE input. A "low"  
level on this input will tri-state its corresponding Q-bus. In this way the Q-bus from all chips can be wire-OR'ed.  
Individual TEST STROBE signals to each chip, however, are required.  
Figure 8: 128 X 128 Crosspoint Switch Diagram  
1st 64 Inputs  
2nd 64 Inputs  
Z0 - Z63  
I0 - I63  
A0 - A5  
I64 - I127  
64  
A0 - A5  
64  
64  
64  
VSC864  
VSC864  
1st 64  
Outputs  
Z0 - Z63  
Z0 - Z63  
TRI  
D0 - D5  
TRI  
TRI  
D0 - D5  
D0 - D5  
6
6
1
2
I64 - I127  
I0 - I63  
64  
64  
I0 - I63  
A0 - A5  
I64 - I127  
A0 - A5  
Z64 - Z127  
64  
Z64 - Z127  
64  
2nd 64  
Outputs  
VSC864  
VSC864  
TRI  
TRI  
D0 - D5  
D0 - D5  
6
6
3
4
G52132-0 Rev. 2.0  
® VITESSE Semiconductor Corporation  
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