VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC8151
2.488Gb/s SONET/SDH
STS-48/STM-16 Section Terminator
Loss of Frame
A Loss of Frame (LOF) defect is declared (RXLOF active high) when a Severely Errored Frame (SEF) con-
dition persists for 3ms (R6-59). The LOF state detection is based on an integrating timer to prevent sporadic
errors from asserting LOF, such as a periodic 1ms error. An LOF defect is cancelled after an in-frame condition
(SEF low) persists for 3ms (R6-61) because an integrating timer approach has been implemented (O6-62).
Multiple SONET/SDH Rate Functionality
The VSC8151 supports three SONET/SDH rates: STS-48/STM-16, STS-12/STM-4, and STS-3/STM-1.
The user is responsible for rate-provisioning the device by setting the RATESEL register (See Table 2). The
device requires clocks RXSCLKIN+/- and TXSCLKIN+/- to match the selected data rate in order for internal
circuitry to function correctly. The RATESEL register changes the expected frame length of the received signal
and selects the characteristics of the outgoing traffic or AIS signal. LOF integration timing remains 3ms regard-
less of selected SONET/SDH rate.
Descrambler
Framed SONET/SDH bytes are descrambled using a frame synchronous descrambler with generating poly-
nomial 1 + X6 + X7 and a sequence length of 127. The scrambling algorithm is reset to an all 1’s state immedi-
ately following the Z0 byte (last channel of first row, third column). The A1, A2, and J0/Z0 bytes are not
descrambled (R5-6). The descrambler can be disabled by setting the MISC register appropriately.
B1 Error Monitoring
The bit-interleaved parity (BIP-8) error detection code (B1) will be calculated for every received frame
before descrambling and compared to the descrambled B1 value in the following frame (R3-16). The results of
this calculation are used to generate a B1 parity mask that is output using the overhead output interface. The cal-
culated B1 parity used to do this comparison can be substituted in the received data stream and output. This
effectively ‘corrects’ the B1 byte and prevents the same B1 errors from being detected downstream.
B2 Error Monitoring
Incoming B2 errors for the first STS-1 are monitored and detected. This circuitry is not designed to supply
B2 error rate monitoring but exists to provide support for modification of the overhead bytes of the line over-
head. Incoming B2 parity must be determined because modification of the line overhead requires that the B2
byte for the first STS-1 be re-calculated. If the line overhead is not being modified by the user then the B2 error
monitoring still takes place and the B2 errormask is output.
Overhead Output
The 9 bytes of the SONET section overhead and the 18 bytes in the first channel of the line overhead (See
Figure 7) are made available to the user through the overhead output interface RXOHOUT[7:0], RXOHCLK,
and RXFPOUT. Two additional bytes containing the results of the B1 and B2 parity error detection are also out-
put. These 29 bytes are output from the RXOHOUT port, each accompanied by a pulse of RXOHCLK. The 27
overhead bytes are output in the order they are received, with a pulse on RXFPOUT appearing after the J0 byte.
RXFPOUT is used to provide a reference point for the 29 byte output sequence of overhead bytes and clocks
G52225-0, Rev. 2.9
12/1/99
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VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
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