VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC8151
2.488Gb/s SONET/SDH
STS-48/STM-16 Section Terminator
Data present on the TXOHIN[7:0] bus is written to the internal register addressed by TXADDR[5:0] on the ris-
ing edge of TXWRENA. Assertion of TXOHWI (active high) during the overhead byte write cycle inhibits the
modification of the addressed overhead byte.
A1/A2 Boundary Modification
Only the first A1 and A2 bytes of the SONET/SDH can be modified. The A1 byte can be replaced with user
defined data without affecting the framing algorithms of subsequent VSC8151 devices. An F6H byte can be re-
substituted before exiting the subsequent VSC8151, effectively creating an in-band 64kb/s messaging channel.
The A2 byte could be replaced by the user to intentionally corrupt the A1/A2 boundary and output a data stream
that causes downstream network equipment to lose frame lock and enter alarm states.
BIP-8 Recalculation & Modification
The TXOHIN[7:0] information written to the B1 and B2 address location does not replace the outgoing BIP
byte. The 8 bits form an XOR mask that will intentionally induce BIP errors into the outgoing data stream. A
TXOHIN[7:0] word such as B2H would corrupt the BIP byte at bits 1, 4, 5, 7, and a downstream device will
observe four parity errors. A TXOHIN[7:0] word of 00H will induce no parity errors, but will replace the BIP
byte with a recalculated value. Setting the TXOHWI bit at the B1 or B2 location will prevent the BIP byte from
being modified or corrected.
Note that if there is any modification to the transport overhead it is necessary for the B1 byte to be corrected
in order to prevent downstream parity errors. The B2 byte needs to be corrected if any changes are made to the
line overhead for the same reason.
Errors can be intentionally induced to the B2 channel to compensate for the lack of complete B2 error mon-
itoring. Modifying the line overhead requires that the B2 byte in the first STS-1 be corrected, but this has the
effect of artificially lowering the observed B2 error rate at subsequent line termination equipment (LTE). Cor-
recting the B2 byte in the first STS-1 position will result in a 1/48th, 1/12th, or 1/3rd reduction depending on the
provisioned SONET/SDH rate. Monitoring received B2 errors on the RXOHOUT[7:0] B2 errormask and re-
writing this errormask to the B2 address will keep the outgoing B2 error rate consistent with the received B2
error rate.
Alarm Indication Signal (AIS) Overhead Modification
Transport overhead modification procedures are identical for AIS transmission mode. TXFPOUT is
sourced from the frame counters resident within the receive framing circuitry during non-AIS transmission
mode. During an AIS condition valid SONET/SDH data is no longer being received, resulting in the part enter-
ing a LOF or LOS state. Counters in the receive framing block will be invalid during this time, therefore when
AIS is asserted the TXFPOUT signal is sourced from a redundant set of frame counters present within the AIS
generation state machine. The frame counters for AIS block are separate from the receive framing circuitry, and
as a result the TXFPOUT signal will be in an unknown state during a AIS mode transition, but will become
periodic again after 125us. User logic should anticipate a late or early TXFPOUT pulse when switching in and
out of AIS mode.
G52225-0, Rev. 2.9
12/1/99
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VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
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