VITESSE
SEMICONDUCTOR CORPORATION
2.488Gb/s SONET/SDH
Advance Product Information
STS-48/STM-16 Section Terminator
VSC8151
(See Figure 7). It is suggested that RXOHCLK be used to clock an external counter with RXFPOUT providing
a counter reset. This allows the counter value to be correlated to a specific output byte and to be used as a write
address for a register file.
Figure 7: Functional Overhead Output Timing
= delay
RXOHOUT[7:0]
M0
E2
A1
A2
J0
B1
E1
F1
B1MASK
S1
RXOHCLK
RXFPOUT
The additional two bytes are parity error masks that indicate the number of received B1 and B2 errors.
These bytes contain a parity error-mask of the results of the BIP calculation. Incoming parity errors are desig-
nated by a ‘1’ in the corresponding bit position. A B1 or B2 error mask byte of 00H indicates no received parity
errors for that frame, and a byte of 13H would indicate 3 of 8 bits were errored. The B1 error mask appears
immediately after the F1 user byte is output and the B2 error mask appears immediately after the K2 APS byte
is output.
The RXOHOUT[7:0] output is undefined when SEF is high. RXFPOUT and RXOHCLK are functions of
the received data being properly framed and will also be indeterminate during a SEF or LOS condition.
SONET/SDH Modification Circuitry Overview
The modification circuitry receives frame aligned data from the monitoring circuitry or from an internal
state machine that generates a section AIS signal. The transport overhead of either signal can be modified by the
user, including the insertion of recalculated B1 parity. These features encompass the requirements for perform-
ing section termination, as well as allowing the modification of line overhead bytes such as K1/K2 and the line
DCC bytes.
Overhead Write Interface
The 9 bytes of the section overhead and the 18 bytes of the first channel of the line overhead can be replaced
with user defined bytes or allowed to pass through the part unchanged. The overhead write interface makes use
of an internal 32 byte register file for storing the 27 overhead modifier bytes as well as providing internal con-
figuration registers. TXWRENA, TXADDR[5:0], TXOHWI, and TXOHIN[7:0] are the write interface inputs.
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VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52225-0, Rev. 2.9
12/1/99
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
