VITESSE
SEMICONDUCTOR CORPORATION
2.488Gb/s SONET/SDH
Advance Product Information
STS-48/STM-16 Section Terminator
VSC8151
Figure 14: Serial Data Output Timing Diagram
TRXSCLKIN
RXSCLKIN+
RXSCLKIN-
TTXSOUT
RXSLBOUT+
RXSLBOUT-
Table 13: Serial Data Output Timing
Parameter
Description
Serial Receive clock period
Min
Typ
Max
Units
TRXSCLKIN
401.9
-
-
ps
Propagation delay from rising edge of TXSCLKIN+/- to
output edge of TXSOUT+/-
TTXSOUT
430
-
630
ps
Figure 15: Parallel Data Output Timing Diagram
TPOUTCLK
POUTCLK
TP
RXPOUT[15:0]
Table 14: Serial Data Output Timing
Parameter
Description
Min
Typ
Max
Units
TPOUTCLK
Parallel output clock period
103.2
-
6.45
ns
Propagation delay from falling edge of POUTCLK to
output edge of RXPOUT[15:0]
TP
-.55
-
1.75
ns
Note: Parallel output clock is synchronously generated 50/50 1/16th the frequency of the serial clock input (RXSCLKIN)
Page 18
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52225-0, Rev. 2.3
8/16/99
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
