VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
2.488Gb/s SONET/SDH
STS-48/STM-16 Section Terminator
VSC8151
Figure 12: Serial Data Input Timing Diagram
TRXSCLKIN
RXSCLKIN-
RXSCLKIN+
TRXSSU TRXSH
RXSIN+
RXSIN-
Table 11: Serial Data Input Timing
Parameter
Description
Serial Receive clock period
Min
Typ
Max
Units
TRXSCLKIN
401.9
-
-
ps
Serial Receive input data RXSIN setup time with respect
to falling edge of RXSCLKIN+
TRXSSU
TRXSH
100
75
-
-
-
-
ps
ps
Serial Receive input data RXSIN hold time with respect
to falling edge of RXSCLKIN+
Figure 13: Parallel Data Input Timing Diagram
TPOUTCLK
POUTCLK
TRXPSU TRXPH
RXPIN[15:0]
Table 12: Serial Data Input Timing
Parameter
Description
Min
Typ
Max
Units
TPOUTCLK
Parallel output clock period
103.2
-
6.45
ns
Parallel receive input data RXPIN setup time with
respect to falling edge of POUTCLK output
TRXPSU
TRXPH
2.4
1.0
-
-
-
-
ns
ps
Parallel receive input data RXPIN hold time with respect
to falling edge of POUTCLK output
Note: Parallel output clock is synchronously generated 50/50 1/16th the frequency of the serial clock input (RXSCLKIN)
G52225-0, Rev. 2.3
VITESSE SEMICONDUCTOR CORPORATION
Page 17
8/16/99
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
