VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
Multi-Rate SONET/SDH
Clock and Data Recovery IC
VSC8122
Table 2: Reference Frequency
Reference Frequency
REF_SEL0
REF_SEL1
19.44MHz (19.53MHz)
38.88MHz (39.06MHz)
77.76MHz (78.13MHz)
155.52MHz (156.25MHz)
0
1
0
1
0
0
1
1
Loop Filter
The Phase-Lock Loop (PLL) on the VSC8122 employs two external capacitors. The PLL design is fully
differential, therefore the loop filter must also be fully differential. One capacitor should be connected between
FILTAO and FILTAI, with the other connected between FILTAON and FILTAIN. Recommended capacitors are
low-inductance 1.0µF (0603 or 0805) ceramic SMT X7R devices, 6.3 WVDC or greater, with tolerance of 10%
or better.
AC Characteristics (Over recommended operating conditions)
Table 3: AC Characteristics
Parameters
tpd
Description
Min
Typ
Max
Units
Conditions
Center of output data eye from
rising edge of CO+
-75
—
+75
ps
tr,tf
tr,tf
DO rise and fall times
CO rise and fall times
—
—
—
—
150
135
ps
ps
20% to 80% into 50Ω load.
20% to 80% into 50Ω load.
Measured at the HS data output for
Jitter Generation (12kHz-
20MHz)
Jittergen
—
—
3.6
ps - rms jitter in the 12kHz - 20MHz band.
Assume 1.2ps rms input data jitter.
Jittertol
LBW
Jitter Tolerance
Loop Bandwidth
Jitter Peaking
—
—
—
—
—
—
—
2.0
0.1
—
Exceeds SONET/SDH mask
MHz -3dB point of jitter transfer curve
dB
Jitterpeak
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52228-0, Rev 4.1
01/05/01
Page 5
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