VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
2.488GHz SONET/SDH
Clock Generator
VSC8121
Example Set-Up
The figure below shows one possible set-up using the VSC8121 Evaluation Board and recommended con-
nections listed above. In this configuration, the device receives its reference clock input from an external signal
generator supplying a 900mV(RMS) signal. As an alternative, a crystal oscillator may be used instead to pro-
vide this reference. The CO and CON (High-Speed Clock True and Complement) and LSCLK signals may then
be viewed with the scope, as shown on channels 1 through 3. Alternatively, if only one output is being viewed
by the scope, a 50ohm termination should be used on the remaining output to achieve more accurate measure-
ments.
Figure 9: Example Equipment Set-up Using the VSC8121 Evaluation Board
CLOCKOUT
(51.84, 77.76 or 155.52MHz)
CLOCKOUTN
Pattern
Generator
TRIGGER
Digital Sampling
Scope
900mV(RMS)
CH1
CH2
TRIGGER
VEE VCC
(0V) (3.3V)
Reference Clock (REFCLK)
J5
J7
Low Speed Clock (LSCLK)
Optional
Crystal
J9
J8
High-Speed Clock (CO)
VSC8121
Eval Board
High-Speed Clock Complement (CON)
The intent of this section is to answer the most common questions surrounding the use of the VSC8121
Evaluation Board. Please contact your local sales office if there are any additional details that Vitesse Semicon-
ductor can provide to help you make more efficient use of your evaluation board.
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 16
G52163-0, Rev 4.2
04/16/01
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
