VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
2.488GHz SONET/SDH
Clock Generator
VSC8121
Table 10: REFSEL [0,1] Switch Settings (S1, S2) For Selected Reference Frequency
REFSEL[0]
(S1)
REFSEL[1]
(S2)
Selected Reference Frequency
0
0
1
0
51.84MHz
77.76MHz
155.52MHz
1
Don’t Care
As reiterated above, the selected reference frequency is determined by the TTL inputs REFSEL[0] and
REFSEL[1]. The board can be made to operate with a REFCLK of either 51.84MHz or 77.76MHz by closing or
opening the appropriate connections at locations S1 and S2. As indicated in Table 10, S1 controls REFSEL[0],
and S2 controls REFSEL[1]. Closing one of these connections shorts the corresponding REFSEL pin to VEE.
You may either place a permanent short across the desired pin, or place a switch in both locations to leave the
option of toggling to different reference clock settings. (As an example, to configure the device to expect a
77.76MHz frequency, you would place a short or close the switch across S1 and leave S2 open.)
Recommended Evaluation Board Connections
Chabin to Banana Jack Connections
• JP1 (2nd position) to positive terminal of VS1
• JP1 (4th position) to negative terminal of VS1
(Optionally, microclip or other connectors can be used to route power as deemed practical by the customer)
SMA Cable Connections
• J5 (REFCLK) to the RF Out port of the Signal Generator, -or- you may leave J5 unconnected and place a
crystal oscillator in location U2 (see the Using A Crystal Oscillator section below)
• J7 (LSCLK) to the external TRIGGER input of the Digital Oscilloscope
• J8 (CON) to Ch 1 of the Digital Oscilloscope
• J9 (CO) to Ch 2 of the Digital Oscilloscope
NOTE: Ports not listed are not required for normal operation of the device, and should be left unconnected.
Using a Crystal Oscillator
The board provides an option for a crystal oscillator if it is not desired to drive the reference clock signal
with a signal generator or other device. A telecom-quality 155.52MHz crystal is recommended, since the goal
should be to introduce the least amount of jitter into the input as possible. Certain frequencies of jitter (those
below the loop bandwidth of the PLL) introduced at the REFCLK input will appear directly at the output of the
device.
G52163-0, Rev 4.2
04/16/01
Page 15
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