VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8116
Parameter
T
RXCLK
T
RXSU
T
RXH
Receive clock period
ATM/SONET/SDH 622/155Mb/s Transceiver
Mux/Demux with Integrated Clock Generation
Table 5: Receive High Speed Data Input Timing Table
(STS-3
Operation)
Description
Serial data setup time with respect to RXCLKIN
Serial data hold time with respect to RXCLKIN
Min
-
1.5
1.5
Typ
6.43
-
-
Max
-
-
-
Units
ns
ns
ns
Figure 8: Transmit Data Input Timing Diagram
T
CLKOUT
TXLSCKOUT
T
INSU
T
INH
TXIN [7:0]
Table 6: Transmit Data Input Timing Table
(STS-12
Operation)
Parameter
T
INSU
T
INH
Description
Transmit data setup time with respect to TXLSCKOUT
Transmit data hold time with respect to TXLSCKOUT
Min
1.0
1.0
Typ
-
-
Max
-
-
Units
ns
ns
Table 7: Transmit Data Input Timing Table
(STS-3
Operation)
Parameter
T
INSU
T
INH
Description
Transmit data setup time with respect to TXLSCKOUT
Transmit data hold time with respect to TXLSCKOUT
Min
1.0
1.0
Typ
-
-
Max
-
-
Units
ns
ns
Note: Duty cycle for TXLSCKOUT is 50% +/- 10% worst case
G52220-0, Rev 4.1
1/8/00
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VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 9
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