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VSC8116 参数 Datasheet PDF下载

VSC8116图片预览
型号: VSC8116
PDF下载: 下载PDF文件 查看货源
内容描述: ATM / SONET / SDH 622 /为155Mb / s的收发器复用/解复用,集成时钟发生器 [ATM/SONET/SDH 622/155Mb/s Transceiver Mux/Demux with Integrated Clock Generation]
分类和应用: 时钟发生器异步传输模式ATM
文件页数/大小: 20 页 / 361 K
品牌: VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
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VITESSE
SEMICONDUCTOR CORPORATION
ATM/SONET/SDH 622/155Mb/s Transceiver
Mux/Demux with Integrated Clock Generation
Data Sheet
VSC8116
Clock Multiplier Unit
The VSC8116 uses an integrated phase-locked loop (PLL) for clock synthesis of the 622MHz high speed
clock used for serialization in the transmitter section. The PLL is comprised of a phase-frequency detector
(PFD), an integrating operation amplifier and a voltage controlled oscillator (VCO) configured in classic feed-
back system. The PFD compares the selected divided down version of the 622MHz VCO (CMUFREQSEL
selects divide-by ratios of 8 or 32, see Table 2) and the reference clock. The integrator provides a transfer func-
tion between input phase error and output voltage control. The VCO portion of the PLL is a voltage controlled
ring-oscillator with a center frequency of 622MHz.
The reactive elements of the integrator are located off-chip and are connected to the feedback loop of the
amplifier through the CP1, CP2, CN1 and CN2 pins. The configuration of these external surface mounted
capacitors is shown in Figure 6. Table 1 shows the recommended external capacitor values for the configurable
reference frequencies.
Good analog design practices should be applied to the board design for these external components. Tightly
controlled analog ground and power planes should be provided for the PLL portion of the circuitry. The dedi-
cated PLL power (VDDA) and ground (VSSA) pins should have quiet supply planes to minimize jitter genera-
tion within the clock synthesis unit. This is accomplished by either using a ferrite bead or a C-L-C choke (π
filter) on the (VDDA) power pins. Note: Vitesse recommends a (π filter) C-L-C choke over using a ferrite bead.
All ground planes should be tied together using multiple vias.
Table 1: Recommended External Capacitor Values
Reference
Frequency
[MHz]
19.44
77.76
Divide Ratio
32
8
CP
0.1
0.1
CN
0.1
0.1
Type
X7R
X7R
Size
0603/0805
0603/0805
Tol.
+/-10%
+/-10%
Page 6
©
VITESSE
SEMICONDUCTOR CORPORATION
G52220-0, Rev 4.1
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
1/8/00