VITESSE
SEMICONDUCTOR CORPORATION
ATM/SONET/SDH 622/155Mb/s Transceiver
Mux/Demux with Integrated Clock Generation
Table 3: Clock Multiplier Unit Performance
Name
RCd
RCj
RCj
RC
f
OCj
OCj
OCfrange
OCd
(1)
(2)
(3)
Data Sheet
VSC8116
Min
40
(1)
Description
Reference clock duty cycle
Reference clock jitter (RMS) @ 77.76 MHz ref
(1)
Reference clock jitter (RMS) @ 19.44 MHz ref
Reference clock frequency tolerance
(2)
(3)
Typ
Max
60
13
5
Units
%
ps
ps
ppm
ps
ps
MHz
%
-20
+20
8
15
Output clock jitter (RMS) @ 77.76 MHz ref
Output frequency
Output clock duty cycle
Output clock jitter (RMS) @ 19.44 MHz ref
(3)
620
40
624
60
These Reference Clock Jitter limits are required for the outputs to meet SONET system level jitter requirements
(< 10 mUIrms)
Needed to meet SONET output frequency stability requirements
Measured
Note: Jitter specification is defined utilizing a 12KHz - 5MHz LP-HP single pole filter.
AC Timing Characteristics
Figure 7: Receive High Speed Data Input Timing Diagram
T
RXCLK
RXCLKIN+
RXCLKIN-
T
RXSU
RXDATAIN+
RXDATAIN-
T
RXH
Table 4: Receive High Speed Data Input Timing Table
(STS-12
Operation)
Parameter
T
RXCLK
T
RXSU
T
RXH
Receive clock period
Serial data setup time with respect to RXCLKIN
Serial data hold time with respect to RXCLKIN
Description
Min
-
250
250
Typ
1.608
-
-
Max
-
-
-
Units
ns
ps
ps
Page 8
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VITESSE
SEMICONDUCTOR CORPORATION
G52220-0, Rev 4.1
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
1/8/00
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