VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
ATM/SONET/SDH 622/155Mb/s Transceiver
Mux/Demux with Integrated Clock Generation
VSC8116
Figure 9: Receive Data Output Timing Diagram
TRXCLKIN
RXCLKIN+
RXCLKIN-
TRXLSCK
RXLSCKOUT
RXOUT [7:0]
FP
A1
A2
A2
A2
A2
TRXVALID
Table 8: Receive Data Output Timing Table (STS-12 Operation)
Parameter
Description
Min
Typ
Max
Units
TRXCLKIN
TRXLSCK
Receive clock period
-
-
1.608
12.86
-
-
ns
ns
Receive data output byte clock period
Time data on RXOUT [7:0] and FP is valid before and
after the rising edge of RXLSCKOUT
TRXVALID
TPW
4.0
-
-
-
-
ns
ns
Pulse width of frame detection pulse FP
12.86
Table 9: Receive Data Output Timing Table (STS-3 Operation)
Parameter
Description
Min
Typ
Max
Units
TRXCLKIN
TRXLSCKT
Receive clock period
-
-
6.43
-
-
ns
ns
Receive data output byte clock period
51.44
Time data on RXOUT [7:0] and FP is valid before and
after the rising edge of RXLSCKOUT
TRXVALID
TPW
22
-
-
-
-
ns
ns
Pulse width of frame detection pulse FP
51.44
Page 10
VITESSE SEMICONDUCTOR CORPORATION
G52220-0, Rev 4.1
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
1/8/00
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
