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VSC8116QP2 参数 Datasheet PDF下载

VSC8116QP2图片预览
型号: VSC8116QP2
PDF下载: 下载PDF文件 查看货源
内容描述: ATM / SONET / SDH 622 /为155Mb / s的收发器复用/解复用,集成时钟发生器 [ATM/SONET/SDH 622/155Mb/s Transceiver Mux/Demux with Integrated Clock Generation]
分类和应用: 时钟发生器ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
文件页数/大小: 20 页 / 361 K
品牌: VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
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VITESSE
SEMICONDUCTOR CORPORATION
ATM/SONET/SDH 622/155Mb/s Transceiver
Mux/Demux with Integrated Clock Generation
Data Sheet
VSC8116
PLL clock multiplier. Optics have either a PECL or TTL output, usually called “SD” (Signal Detect) or “FLAG”
indicating either a lack of or presence of optical power. Depending on the optics manufacture this signal is
either active high or active low polarity. If the optics Signal Detect or FLAG output is a “TTL” signal, it should
be connected to LOSTTL. If it’s a “PECL” signal it should be connected through a “PECL” to “TTL” translator
(such as the Motorola “MC100ELT21”) which then drives LOSTTL. The follow on part to VSC8116 is the
VSC8117, in this device the signal LOSTTL has been changed to LOSPECL, a PECL input.
Facility Loopback
The Facility Loopback function is controlled by the FACLOOP signal. When the FACLOOP signal is set
high, the Facility Loopback mode is activated and the high speed serial receive data (RXDATAIN) is presented
at the high speed transmit output (TXDATAOUT). See Figure 3. In Facility Loopback mode the high speed
receive data (RXDATAIN) is also converted to parallel data and presented at the low speed receive data output
pins (RXOUT [7:0]). The receive clock (RXCLKIN) is also divided down and presented at the low speed clock
output (RXLSCKOUT).
Figure 3: Facility Loopback Data Path
RXDATAIN
D
Q
1:8
Serial to
Parallel
D
Q
RXOUT[7:0]
RXCLKIN
1
÷8
Q
D
Q
D
RXLSCKOUT
TXIN[7:0]
TXDATAOUT
0
8:1
Parallel to
Serial
1
0
PLL
FACLOOP
Equipment Loopback
The Equipment Loopback function is controlled by the EQULOOP signal. When the EQULOOP signal is
set high, the Equipment Loopback mode is activated and the high speed transmit data generated from the paral-
lel to serial conversion of the low speed data (TXIN [7:0]) is selected and converted back to parallel data in the
receiver section and presented at the low speed parallel outputs (RXOUT [7:0]). See Figure 4. The internally
generated 155MHz/622MHz clock is used to generate the low speed receive clock output (RXLSCKOUT). In
Equipment Loopback mode the transmit data (TXIN [7:0]) is serialized and presented at the high speed output
(TXDATAOUT).
Page 4
©
VITESSE
SEMICONDUCTOR CORPORATION
G52220-0, Rev 4.1
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
1/8/00