VSC8115
Data Sheet
P
ACKAGE
I
NFORMATION
VDDA
DATAIN+
DATAIN–
VSSA
LOCKDET
STS12
REFCLK
LOCKREFN
VSS
VDD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
VDDA
VSSA
CAP+
CAP–
BYPASS
SD
DATAOUT+
DATAOUT–
CLKOUT+
CLKOUT–
VSC8115
Top View
16
15
14
13
12
11
Figure 6. Pin Diagram for 20-Pin TSSOP (YA, YA-02, YA-03, YA-T)
Table 12. Pin Identifications for 20-Pin TSSOP (YA, YA-02, YA-03, YA-T)
Pin
1
2
3
4
5
Signal
VDDA
DATAIN+
DATAIN–
VSSA
LOCKDET
O
I
I
I/O
Type
Pwr
LVDS/
PECL
LVDS/
PECL
Pwr
LVPECL
Description
+3.3V power supply for high-speed I/Os and on-chip PLL blocks.
Receive Data Input, True. The high-speed output clock (CLKOUT±) is
recovered from this high-speed differential input data.
Receive Data Input, Complement. The high-speed output clock (CLKOUT±)
is recovered from this high-speed differential input data.
Ground pin for low-speed I/Os and on-chip digital PLL blocks.
Active HIGH to indicate that the PLL is locked to serial data input and valid
clock and data are present at the serial outputs (DATAOUT± and CLKOUT±).
The LOCKDET will go inactive under the following conditions:
• If SD is set LOW
• If LOCKREFN is set LOW
• If the VCO has drifted away from the local reference clock, REFCLK, by
more than 500ppm.
6
7
STS12
REFCLK
I
I
LVTTL
LVTTL
STS-12 or STS-3 Mode Selection. Set HIGH to select the STS-12 operation.
Set LOW to select the STS-3 operation.
Local Reference Clock Input for the CRU, 19.44MHz. REFCLK is used for the
PLL phase adjustment during power up and also serves as a stable clock
source in the absence of serial input data.
Lock to REFCLK Input. When set LOW, it holds the CLKOUT± output to
within ±500ppm of the REFCLK input and forces the DATAOUT± output to the
LOW state.
Ground pin for low-speed I/Os and on-chip digital CMOS blocks.
+3.3V power supply for low-speed I/Os and on-chip digital CMOS blocks.
High-Speed Clock Output, Complement. This clock is recovered from the
receive data input (DATAIN±) and can be configured as either a LVDS or
LVPECL signal.
8
LOCKREFN
I
LVTTL
9
10
11
VSS
VDD
CLKOUT–
O
Pwr
Pwr
LVDS/
LVPECL
9 of 12
G52272, Rev 4.2
5/14/03
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
