VSC8115
Data Sheet
Table 12. Pin Identifications for 20-Pin TSSOP (YA, YA-02, YA-03, YA-T) (continued)
Pin
Signal
I/O
Type
Description
12
CLKOUT+
O
LVDS/
High-Speed Clock Output, True. This clock is recovered from the receive data
LVPECL input (DATAIN ) and can be configured as either a LVDS or LVPECL signal.
13
DATAOUT–
O
LVDS/ High-Speed Data Output, Complement. This is the retimed version of the
LVPECL receive data input (DATAIN ) and can be configured as either a LVDS or
LVPECL signal.
14
15
DATAOUT+
SD
O
I
LVDS/
High-Speed Data Output, True. This is the retimed version of the receive data
LVPECL input (DATAIN ) and can be configured as either a LVDS or LVPECL signal.
LVPECL Signal Detect. SD should be connected to the SD output on the optical
module. SD is active HIGH. When SD is set HIGH, it means there is sufficient
optical power. When SD is set LOW to indicate an LOS condition, the
CLKOUT output signal will be held to within +500ppm of the RECLK input.
Additionally, the DATAOUT will be held in the LOW state.
16
17
BYPASS
I
I
LVTTL
Analog
Used for production testing. Set to V for normal operation.
SS
CAP–
External Loop Filter Input, Complement. The loop filter capacitor should be
connected to these pins. The capacitor value should be 1.0µF 10%.
18
CAP+
I
Analog
External Loop Filter Input, True. The loop filter capacitor should be connected
to these pins. The capacitor value should be 1.0µF 10%.
19
20
VSSA
VDDA
Pwr
Pwr
Ground pin for low-speed I/Os and on-chip digital PLL blocks.
+3.3V power supply for high-speed I/Os and on-chip PLL blocks.
10 of 12
G52272, Rev 4.2
5/14/03
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
