VITESSE
SEMICONDUCTOR CORPORATION
ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery
Data Sheet
VSC8114
Loop Timing
LOOPTIM0 mode bypasses the CMU when the LOOPTIM0 input is asserted high. In this mode the CMU
is bypassed by using the receive clock (RXCLKIN), and the entire part is synchronously clocked from a single
external source.
Parity
An even parity input (TXINP) is provided for the byte-wide transmit data. This input, along with byte-wide
data, is clocked into the VSC8114 on the rising edge of TXLSCKIN. Parity is calculated on the clocked in byte-
wide data and compared to the clocked in parity input. A parity error is reported on the next TXLSCKIN rising
edge on TXPERR. For no parity errors to result, TXINP must be logic 1 when on an odd number of bits in the
TXIN[7:0] are logic 1; otherwise, it must be logic 0.
Even parity is calculated and clocked out along with byte-wide receive data (RXOUT[7:0]) on RXOUTP.
RXOUTP is a logic 1 when an odd number of bits on RXOUT[7:0] are logic 1; ohterwise, it is logic 0.
Clock Synthesis
The VSC8114 uses an integrated phase-locked loop (PLL) for clock synthesis of the 622MHz high speed
clock used for serialization in the transmitter section. The PLL is comprised of a phase-frequency detector
(PFD), an integrating operation amplifier and a voltage controlled oscillator (VCO) configured in classic feed-
back system. The PFD compares the selected divided down version of the 622MHz VCO (select pin REFSEL
selects divide-by ratios of 8 and 32, see Table 11) and the reference clock. The integrator provides a transfer
function between input phase error and output voltage control. The VCO portion of the PLL is a voltage con-
trolled ring-oscillator with a center frequency of 622MHz.
The reactive elements of the integrator are located off-chip and are connected to the feedback loop of the
amplifier through the CP1, CP2, CN1 and CN2 pins. The configuration of these external surface mounted
capacitors is shown in Figure 6. Table 1 shows the recommended external capacitor values for the configurable
reference frequencies.
Good analog design practices should be applied to the board design for these external components. Tightly
controlled analog ground and power planes should be provided for the PLL portion of the circuitry. The dedi-
cated PLL power (VDDANA) and ground (VSSANA) pins should have quiet supply planes to minimize jitter
generation within the clock synthesis unit. This is accomplished by either using a ferrite bead or a C-L-C choke
(π filter) on the (VDDANA) power pins. Note: Vitesse recommends a (π filter) C-L-C choke over using a ferrite
bead. All ground planes should be tied together using multiple vias.
Reference Clocks
Note that the CMU uses a differential PECL reference clock input to achieve optimum jitter performance.
The CRU has the option of either using the CMU’s reference clock or its own independent reference clock
CRUREFCLK. This is accomplished with the control signal CRUREFSEL. The CRUREFCLK should be used
if the system is being operated in either a regeneration or loop timing mode. In either of these modes the quality
of the CRUREFCLK is not a concern, thus it can be driven by a simple 77.76MHz crystal, the key is its indepen-
dence from the CMU’s reference clock.
Page 6
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52185-0, Rev 4.0
11/1/99
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
