VITESSE
SEMICONDUCTOR CORPORATION
ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery
Data Sheet
VSC8114
detector circuit which is used to provide frame pluses during the A1, A2 boundary in the serial to parallel con-
verter. This only occurs when OOF is high. Both internal and external LOS functions are supported.
The VSC8114 provides the parity error detection and generation for the 8 bit data bus. On the receive side,
the parity of the 8 bit data outputs is generated. On the transmit side, the parity of the 8 bit data input is calcu-
lated and compared with the received parity input.
VSC8114 Block Diagram
EQULOOP
RESET
D Q
0
1
0
1
Divide-by-8
Parity Chk
TXDATAOUT+/-
Q D
1
0
1
0
FACLOOP
Divide-by-8
8:1
MUX
REG
8
TXIN[7:0]
TXLSCKIN
TXLSCKOUT
RXLSCKOUT
TXPERR
TXINP
1:8
DEMUX
Parity/
REG
8
RXOUT[7:0]
RXOUTP
FRAMER
OOF
FP
1
0
LOOPTIM0
0
1
RXDATAIN+/-
CRUEQLP
0
CRU
REC-CLK
RXCLKIN+/-
DSBLCRU
losdet
0
1
REC-DATA
1
0
1
CMU
REFCLKP+/-
REFSEL
LOSPECL
LOSTTL
LOSDETEN_
0
1
CRUREFCLK
CRUREFSEL
Transmit Section
Byte-wide data is presented to TXIN[7:0] and is clocked into the part on the rising edge of TXLSCKIN.
See Figure 1. The data is then serialized (MSB leading) and presented to the TXDATAOUT+/- pins. The serial
output stream is synchronized to the CMU generated clock which is a phase locked and frequency scaled ver-
Page 2
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VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52185-0, Rev 4.0
11/1/99
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
