VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8114
AC Timing Characteristics
ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery
Figure 8: Receive High Speed Data Input Timing Diagram
T
RXCLK
RXCLKIN+
RXCLKIN-
T
RXSU
RXDATAIN+
RXDATAIN-
T
RXH
Table 3: Receive High Speed Data Input Timing Table
Parameter
T
RXCLK
T
RXSU
T
RXH
Receive clock period
Serial data setup time with respect to RXCLKIN
Serial data hold time with respect to RXCLKIN
Description
Min
-
250
250
Typ
1.608
-
-
Max
-
-
-
Units
ns
ps
ps
Figure 9: Receive Data Output Timing Diagram
T
RXCLKIN
RXCLKIN+
RXCLKIN-
T
RXLSCK
RXLSCKOUT
RXOUT [7:0]
RXOUTP
A1
A2
A2
A2
A2
T
RXVALID
FP
Table 4: Receive Data Output Timing Table
Parameter
T
RXCLKIN
T
RXLSCK
T
RXVALID
T
PW
Receive clock period
Receive data output byte clock period
Time data on RXOUT [7:0], FP, and RXOUTP is valid
before and after the rising edge of RXLSCKOUT
Pulse width of frame detection pulse FP
Description
Min
-
-
4.0
-
Typ
1.608
12.86
-
12.86
Max
-
-
-
-
Units
ns
ns
ns
ns
G52185-0, Rev 4.0
11/1/99
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 9
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