VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
2.5Gb/s 16-Bit
Multiplexer/Demultiplexer Chipset
VSC8061/VSC8062
VSC8062 Demultiplexer AC Characteris tics (Over recommended operating range)
Figure 6: VSC8062 Timing Diagram
tCLK
CLK (CLKN)
High-speed differential clock input
DI (DIN)
High-speed serial data input
tD
CLK16
Parallel data clock output
tD
tBD
D0
D1
D15
Table 2: VSC8062 AC Characteristics
Parameter
Description
Min
Typ
Max
3.0
Units
Conditions
tCLK
tD
Clock period(1)
400
6.4
1.0
ps
ns
ns
BYTE CLK16 period (tCLK x 16)
tDSU
CLK16 falling edge output to valid data
tSU + tH
æ
ö
Phase Margin = 1 – ------------------- ´ 360°
è
ø
tCLK
tDH
180(3)
degrees
Serial data phase timing margin with respect to
high-speed clock(2)
NOTES: (1) If t
changes, all remaining parameters change as indicated by the equations.
CLK
(2) t and t are setup and hold times of the serial data input register.
SU
H
(3) At t
= 400ps.
CLK
G52069-0, Rev 4.3
05/11/01
Page 5
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