VITESSE
SEMICONDUCTOR CORPORATION
2.5Gb/s SONET-Compatible
8-Bit MUX/DEMUX Chipset
Table 2: VSC8022 Demultiplexer AC Characteristics
Parameter
t
C
t
D
t
BD
t
DFP
t
PFP
t
OOFN
t
OOFNPW
Phase
Margin
Clock period
(1)
BYTE clock period (t
D
= t
C
x 8) (framed)
BYTE clock output to valid data
FP rising edge from parallel data output
change from A1 to A2 (t
DFP
= t
D
)
FP pulse width (t
PFP
= t
D
)
OOFN falling edge before A1 chan
ges to A2 (t
OOFN
= t
D
x 4)
OOFN pulse width (t
OOFNPW
= t
D
)
Serial data phase timing margin with respect
to high-speed clock:
t
SU
+
t
H
Phase Margin =
1 – ------------------
360°
-
t
C
3.2
12.8
3.2
Data Sheet
VSC8021/VSC8022
Min
400
3.2
0.5
1.0
3.2
2.0
Description
Typ
Max
Units
ps
ns
ns
ns
ns
ns
ns
Conditions
135
180
degrees
NOTE: (1) If t
C
changes, all the remaining parameters change as indicated by the equations.
DC Characteristics
Table 3: Low Speed ECL Inputs and Outputs
(
Over recommended operating range with internal V
REF,
V
CC
= GND, output load = 50
Ω
to -2.0V)
Parameter
V
OH
V
OL
V
IH
V
IL
∆V
OUT
Description
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
Output voltage swing
Min
-1020
V
TT
-1150
V
TT
0.8
Typ
Max
-700
-1620
-600
-1500
Units
mV
mV
mV
mV
V
Conditions
V
IN
= V
IH
(max) or V
IL
(min)
V
IN
= V
IH
(max) or V
IL
(min)
Guaranteed HIGH signal for
all inputs
Guaranteed LOW signal for
all inputs
Output load 50Ω to V
TT
1.0
1.4
Note: Differential ECL output pins must be terminated identically.
Table 4: High-Speed Inputs and Outputs
(Over recommended operating conditions, V
CC
= GND, Output load = 50Ω to -2.0V)
Parameter
∆V
IN
V
OH
V
OL
∆V
OUT(DATA)
∆V
OUT(clk)
Description
Input voltage swing
Output HIGH voltage
Output LOW voltage
Output voltage swing for data
Output voltage swing for clock
Min
0.8
Typ
1.0
-0.9
-1.8
Max
1.2
Units
V
V
V
Conditions
AC-coupled
Output load, 50Ω to -2.0V
Output load, 50Ω to -2.0V
Output load, 50Ω to -2.0V
Output load, 50Ω to -2.0V
0.6
0.6
0.8
0.7
1.2
1.2
V
V
NOTES: (1) A reference generator is built in to each high-speed input, and these inputs are designed to be AC-coupled.
(2) If a high-speed input is used single-ended, a 150pF capacitor must be connected between the unused high-speed or comple-
ment input and the power supply (V
TT
).
(3) Differential high-speed outputs must be terminated identically.
Page 6
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VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52028-0, Rev 4.1
05/25/01
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
